The present invention relates to electronic devices, and more specifically to electronic device package structures and methods of fabricating the same.
Electronic devices, such as semiconductor dies are conventionally enclosed in plastic packages that protect the semiconductor die from hostile environments and that enable electrical interconnection between the semiconductor die and a next level of assembly, such as a printed circuit board (PCB) or motherboard. The elements of a typical electronic package include a conductive leadframe or substrate, an integrated circuit or semiconductor die, conductive structures, such as bond wires or solder balls that electrically connect pads on the semiconductor die to individual leads of the leadframe or substrate; and a hard plastic encapsulant material that covers the other components and forms an exterior of the semiconductor package commonly referred to as the package body. Portions of the individual leads can be exposed to electrically connect the package to the next level assembly.
Chip scale packaging (“CSP”) is one packaging technique currently used to support end-user demands for increased integration and increased functionality coupled with demands for thinner and smaller footprint packages. One type of CSP device is referred to as a thin substrate CSP device or tsCSP device. FIGS. 3A to 3E show cross-sectional views of a known manufacturing process for fabricating tsCSP style devices.
As shown in FIG. 3A, a cavity 2 is formed in a dual stepped manner on a bottom surface of a leadframe 1. Next, cavity 2 of leadframe 1 is filled with a dielectric material 3 so that a bottom surface of dielectric material 3 is coplanar with the bottom surface of leadframe 1 as shown in FIG. 3B.
Subsequently, an etching process is used to form a desired pattern on the top surface of leadframe 1, as shown in FIG. 3C. During the etching process, portions of the top and side surfaces of leadframe 1 are removed to form multiple independent terminals 4 having a predetermined pattern or array. Dielectric material 3 insulates the independent terminals 4 from each other.
Next, as shown in FIG. 3D, bond pads on a semiconductor chip 5 are attached to independent terminals 4 on the top surface of leadframe 1 using conductive bumps 6. Thereafter, the structure is placed into a molding apparatus and the structure is molded with a molding compound resin 7 as shown in FIG. 3E. Molding compound resin 7 encapsulates semiconductor chip 5 as well as the top surface of leadframe 1. In the completed tsCSP device, independent terminals 4 are exposed through a bottom surface thereof to be mounted to a next level of assembly.
The conventional tsCSP fabrication method of FIGS. 3A-E has several disadvantages. First, the very thin leadframe is very difficult to handle during the etching process and the independent terminals are left unsupported except for the insulation material, which has been found to be very limited and ineffective. The handling problems also affect the step of mounting the semiconductor chip to the independent terminals and the external forces have been found to cause breakage and other failure mechanisms.
Second, because the independent terminals, the insulating material, and the semiconductor chip have different thermal expansion coefficients, warpage has been found to occur during the molding step. This has resulted in delamination, which can occur, for example, at interfaces between the independent terminals and the insulating material.
Third, in the conventional process the independent terminals are etched before the steps of mounting the semiconductor chip and molding the structure. External forces can cause the location of the independent terminals to deviate from desired positions making alignment and placement of the semiconductor chip onto the independent terminals difficult. This can detrimentally impact process cycle time and device reliability.
Accordingly, it is desirable to have a structure and method for forming electronic device package structures including CSP structures and tsCSP structures that address the issues set forth above as well as others.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description.